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LTC2170-12 Datasheet

LTC2170-12 Datasheet

12-Bit, 25Msps Low Power Quad ADCs
Part No.: LTC2170-12
Page: 34 Pages
Size: 1225 KB
Manufacturer: Linear Technology
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Views: 1
Update Time: 2024-12-05 21:12:02
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LTC2170-12 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2170CUKG-12#PBF Tube 45 LTC2170UKG-12 1 52 0°C ~ 70°C 52-Lead (7mm × 8mm) Plastic QFN  
LTC2170CUKG-12#TRPBF Reel 2000 LTC2170UKG-12 1 52 0°C ~ 70°C 52-Lead (7mm × 8mm) Plastic QFN  
LTC2170IUKG-12#PBF Tube 45 LTC2170UKG-12 1 52 -40°C ~ 85°C 52-Lead (7mm × 8mm) Plastic QFN  
LTC2170IUKG-12#TRPBF Reel 2000 LTC2170UKG-12 1 52 -40°C ~ 85°C 52-Lead (7mm × 8mm) Plastic QFN  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2170-12 Datasheet(PDF)

LTC2170-12 Datasheet(Picture)

LTC2170-12 Features

  • 4-Channel Simultaneous Sampling ADC
  • 71dB SNR
  • 90dB SFDR
  • Low Power: 306mW/198mW/160mW Total, 77mW/50mW/40mW per Channel
  • Single 1.8V Supply
  • Serial LVDS Outputs: One or Two Bits per Channel
  • Selectable Input Ranges: 1VP-P to 2VP-P
  • 800MHz Full Power Bandwidth Sample-and-Hold
  • Shutdown and Nap Modes
  • Serial SPI Port for Configuration
  • Pin-Compatible 14-Bit and 12-Bit Versions
  • 52-Pin (7mm × 8mm) QFN Package

LTC2170-12 Applications

  • Communications
  • Cellular Base Stations
  • Software Defined Radios
  • Portable Medical Imaging
  • Multichannel Data Acquisition
  • Nondestructive Testing

LTC2170-12 Description

The LTC2170-12 are 4-channel, simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 71dB SNR and 90dB spurious free dynamic range (SFDR). An ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specifications include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.

The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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