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LTC2294 Datasheet

LTC2294 Datasheet

Dual 12-Bit, 80Msps Low Power 3V ADC
Part No.: LTC2294
Page: 24 Pages
Size: 665 KB
Manufacturer: Linear Technology
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Views: 2
Update Time: 2023-11-21 10:58:09
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LTC2294 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2294IUP#PBF Tube 40 LTC2294UP 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2294IUP#TRPBF Reel 2000 LTC2294UP 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2294IUP#TRMPBF Reel 500 LTC2294UP 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2294CUP#PBF Tube 40 LTC2294UP 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2294CUP#TRPBF Reel 2000 LTC2294UP 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2294CUP#TRMPBF Reel 500 LTC2294UP 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2294 Datasheet(PDF)

LTC2294 Datasheet(Picture)

LTC2294 Features

  • Integrated Dual 12-Bit ADCs
  • Sample Rate: 80Msps
  • Single 3V Supply (2.7V to 3.4V)
  • Low Power: 422mW
  • 70.6dB SNR at 70MHz Input
  • 90dB SFDR at 70MHz Input
  • 110dB Channel Isolation at 100MHz
  • Multiplexed or Separate Data Bus
  • Flexible Input: 1VP-P to 2VP-P Range
  • 575MHz Full Power Bandwidth S/H
  • Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Pin Compatible Family
  • 64-Pin (9mm × 9mm) QFN Package

LTC2294 Applications

  • Wireless and Wired Broadband Communication
  • Imaging Systems
  • Spectral Analysis
  • Portable Instrumentation

LTC2294 Description

The LTC2294 is a 12-bit 80Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2294 is perfect for demanding imaging and communications applications with AC performance that includes 70.6dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency.

DC specs include ±0.4LSB INL (typ), ±0.2LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.

A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. An optional multiplexer allows both channels to share a digital output bus.

A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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