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LTC2292 Datasheet

LTC2292 Datasheet

Dual 12-Bit, 40Msps Low Power 3V ADCs
Part No.: LTC2292
Page: 28 Pages
Size: 996 KB
Manufacturer: Linear Technology
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Views: 2
Update Time: 2023-11-21 11:15:13
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LTC2292 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2292CUP#PBF Tube 40 LTC2292UP 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2292CUP#TRPBF Reel 2000 LTC2292UP 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2292CUP#TRMPBF Reel 500 LTC2292UP 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2292IUP#PBF Tube 40 LTC2292UP 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2292IUP#TRPBF Reel 2000 LTC2292UP 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2292IUP#TRMPBF Reel 500 LTC2292UP 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2292 Datasheet(PDF)

LTC2292 Datasheet(Picture)

LTC2292 Features

  • Integrated Dual 12-Bit ADCs
  • Sample Rate: 65Msps/40Msps/25Msps
  • Single 3V Supply (2.7V to 3.4V)
  • Low Power: 400mW/235mW/150mW
  • 71.3 dB SNR
  • 90dB SFDR
  • 110dB Channel Isolation at 100MHz
  • Multiplexed or Separate Data Bus
  • Flexible Input: 1VP-P to 2VP-P Range
  • 575MHz Full Power Bandwidth S/H
  • Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Pin Compatible Family
  • 64-Pin (9mm × 9mm) QFN Package

LTC2292 Applications

  • Wireless and Wired Broadband Communication
  • Imaging Systems
  • Spectral Analysis
  • Portable Instrumentation

LTC2292 Description

The LTC2292 are 12-bit 40Msps, low power dual 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2292 are perfect for demanding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals at the Nyquist frequency.

DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS.

A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. An optional multiplexer allows both channels to share a digital output bus.

A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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