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LTC2261-14 Datasheet

LTC2261-14 Datasheet

14-Bit, 125Msps Ultra-Low Power 1.8V ADCs
Part No.: LTC2261-14
Page: 34 Pages
Size: 722 KB
Manufacturer: Linear Technology
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Views: 1
Update Time: 2024-04-19 09:54:51
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LTC2261-14 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2261CUJ-14#PBF Tube 61 LTC2261UJ-14 1 40 0°C ~70°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2261CUJ-14#TRPBF Reel 2000 LTC2261UJ-14 1 40 0°C ~70°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2261CUJ-14#TRMPBF Reel 500 LTC2261UJ-14 1 40 0°C ~70°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2261IUJ-14#PBF Tube 61 LTC2261UJ-14 1 40 -40°C ~85°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2261IUJ-14#TRPBF Reel 2000 LTC2261UJ-14 1 40 -40°C ~85°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2261IUJ-14#TRMPBF Reel 500 LTC2261UJ-14 1 40 -40°C ~85°C 40-Lead (6mm × 6mm) Plastic QFN  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2261-14 Datasheet(PDF)

LTC2261-14 Datasheet(Picture)

LTC2261-14 Features

  • 73.4dB SNR
  • 85dB SFDR
  • Low Power: 127mW/106mW/89mW
  • Single 1.8V Supply
  • CMOS, DDR CMOS or DDR LVDS Outputs
  • Selectable Input Ranges: 1VP-P to 2VP-P
  • 800MHz Full-Power Bandwidth S/H
  • Optional Data Output Randomizer
  • Optional Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Serial SPI Port for Configuration
  • Pin Compatible 14-Bit and 12-Bit Versions
  • 40-Pin (6mm × 6mm) QFN Package

LTC2261-14 Applications

  • Communications
  • Cellular Base Stations
  • Software Defined Radios
  • Portable Medical Imaging
  • Multi-Channel Data Acquisition
  • Nondestructive Testing

LTC2261-14 Description

The LTC2261-14 are sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.4dB SNR and 85dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.

The digital outputs can be either full-rate CMOS, doubledata rate CMOS, or double-data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

The ENC+ and ENC inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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