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LTC2257-12 Datasheet

LTC2257-12 Datasheet

12-Bit, 40Msps Ultralow Power 1.8V ADCs
Part No.: LTC2257-12
Page: 34 Pages
Size: 1033 KB
Manufacturer: Linear Technology
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Views: 1
Update Time: 2024-12-05 20:50:25
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LTC2257-12 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2257CUJ-12#PBF Tube 61 LTC2257UJ-12 1 40 0°C ~ 70°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2257CUJ-12#TRPBF Reel 2000 LTC2257UJ-12 1 40 0°C ~ 70°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2257IUJ-12#PBF Tube 61 LTC2257UJ-12 1 40 -40°C ~ 85°C 40-Lead (6mm × 6mm) Plastic QFN  
LTC2257IUJ-12#TRPBF Reel 2000 LTC2257UJ-12 1 40 -40°C ~ 85°C 40-Lead (6mm × 6mm) Plastic QFN  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2257-12 Datasheet(PDF)

LTC2257-12 Datasheet(Picture)

LTC2257-12 Features

  • 71.1dB SNR
  • 88dB SFDR
  • Low Power: 79mW/47mW/34mW
  • Single 1.8V Supply
  • CMOS, DDR CMOS or DDR LVDS Outputs
  • Selectable Input Ranges: 1VP-P to 2VP-P
  • 800MHz Full-Power Bandwidth S/H
  • Optional Data Output Randomizer
  • Optional Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Serial SPI Port for Configuration
  • Pin Compatible 14-Bit and 12-Bit Versions
  • 40-Pin (6mm × 6mm) QFN Package

LTC2257-12 Applications

  • Communications
  • Cellular Base Stations
  • Software Defined Radios
  • Portable Medical Imaging
  • Multi-Channel Data Acquisition
  • Nondestructive Testing

LTC2257-12 Description

The LTC2257-12 are sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 71.1dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.

The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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