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LTC2234 Datasheet

LTC2234 Datasheet

10-Bit, 135Msps ADC
Part No.: LTC2234
Page: 24 Pages
Size: 558 KB
Manufacturer: Linear Technology
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Views: 1
Update Time: 2023-11-15 16:28:09
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LTC2234 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2234CUK#PBF Tube 52 LTC2234UK 1 48 0°C ~ 70°C 48-Lead QFN (7mm x 7mm x 0.75mm)  
LTC2234CUK#TRPBF Reel 2000 LTC2234UK 1 48 0°C ~ 70°C 48-Lead QFN (7mm x 7mm x 0.75mm)  
LTC2234CUK#TRMPBF Reel 500 LTC2234UK 1 48 0°C ~ 70°C 48-Lead QFN (7mm x 7mm x 0.75mm)  
LTC2234IUK#PBF Tube 52 LTC2234UK 1 48 -40°C ~ 85°C 48-Lead QFN (7mm x 7mm x 0.75mm)  
LTC2234IUK#TRPBF Reel 2000 LTC2234UK 1 48 -40°C ~ 85°C 48-Lead QFN (7mm x 7mm x 0.75mm)  
LTC2234IUK#TRMPBF Reel 500 LTC2234UK 1 48 -40°C ~ 85°C 48-Lead QFN (7mm x 7mm x 0.75mm)  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2234 Datasheet(PDF)

LTC2234 Datasheet(Picture)

LTC2234 Features

  • Sample Rate: 135Msps
  • 61dB SNR up to 200MHz Input
  • 75dB SFDR up to 400MHz Input
  • 775MHz Full Power Bandwidth S/H
  • Single 3.3V Supply
  • Low Power Dissipation: 630mW
  • CMOS Outputs
  • Selectable Input Ranges: ±0.5V or ±1V
  • No Missing Codes
  • Optional Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Data Ready Output Clock
  • Pin Compatible Family
  • 48-Pin 7mm × 7mm QFN Package

LTC2234 Applications

  • Wireless and Wired Broadband Communication
  • Cable Head-End Systems
  • Power Amplifier Linearization
  • Communications Test Equipment

LTC2234 Description

The LTC2234 is a 135Msps, sampling 10-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2234 is perfect for demanding communications applications with AC performance that includes 60.5dB SNR and 75dB spurious free dynamic range for signals up to 400MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) and ±0.8LSB INL, ±0.6LSB DNL over temperature. The transition noise is a low 0.12LSBRMS.

A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC+ and ENC inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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