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LTC2220-1 Datasheet

LTC2220-1 Datasheet

12-Bit, 185Msps ADC
Part No.: LTC2220-1
Page: 28 Pages
Size: 622 KB
Manufacturer: Linear Technology
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Views: 5
Update Time: 2023-11-15 15:37:49
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LTC2220-1 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2220CUP-1#PBF Tube 40 LTC2220UP-1 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2220CUP-1#TRPBF Reel 2000 LTC2220UP-1 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2220CUP-1#TRMPBF Reel 500 LTC2220UP-1 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2220IUP-1#PBF Tube 40 LTC2220UP-1 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2220IUP-1#TRPBF Reel 2000 LTC2220UP-1 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2220IUP-1#TRMPBF Reel 500 LTC2220UP-1 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2220-1 Datasheet(PDF)

LTC2220-1 Datasheet(Picture)

LTC2220-1 Features

  • Sample Rate: 185Msps
  • 67.5dB SNR up to 140MHz Input
  • 80dB SFDR up to 170MHz Input
  • 775MHz Full Power Bandwidth S/H
  • Single 3.3V Supply
  • Low Power Dissipation: 910mW
  • LVDS, CMOS, or Demultiplexed CMOS Outputs
  • Selectable Input Ranges: ±0.5V or ±1V
  • No Missing Codes
  • Optional Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Data Ready Output Clock
  • Pin Compatible Family
  • 64-Pin 9mm × 9mm QFN Package

LTC2220-1 Applications

  • Wireless and Wired Broadband Communication
  • Cable Head-End Systems
  • Power Amplifier Linearization
  • Communications Test Equipment

LTC2220-1 Description

The LTC2220-1 is a 185Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2220-1 is perfect for demanding communications applications with AC performance that includes 67.5dB SNR and 80dB spurious free dynamic range for signals up to 170MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±0.7LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSBRMS.

The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC+ and ENC- inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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