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LTC2209 Datasheet

LTC2209 Datasheet

16-Bit, 160Msps ADC
Part No.: LTC2209
Page: 32 Pages
Size: 593 KB
Manufacturer: Linear Technology
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Views: 1
Update Time: 2025-01-02 14:47:39
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LTC2209 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2209CUP#PBF Tube 40 LTC2209UP 1 64 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2209CUP#TRPBF Reel 2000 LTC2209UP 1 64 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2209IUP#PBF Tube 40 LTC2209UP 1 64 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2209IUP#TRPBF Reel 2000 LTC2209UP 1 64 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2209 Datasheet(PDF)

LTC2209 Datasheet(Picture)

LTC2209 Features

  • Sample Rate: 160Msps
  • 77.3dBFS Noise Floor
  • 100dB SFDR
  • SFDR >84dB at 250MHz (1.5VP-P Input Range)
  • PGA Front End (2.25VP-P or 1.5VP-P Input Range)
  • 700MHz Full Power Bandwidth S/H
  • Optional Internal Dither
  • Optional Data Output Randomizer
  • LVDS or CMOS Outputs
  • Single 3.3V Supply
  • Power Dissipation: 1.53W
  • Clock Duty Cycle Stabilizer
  • Pin-Compatible Family:
  • 64-Pin (9mm × 9mm) QFN Package

LTC2209 Applications

  • Telecommunications
  • Receivers
  • Cellular Base Stations
  • Spectrum Analysis
  • Imaging Systems

LTC2209 Description

The LTC2209 is a 160Msps 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end.

The LTC2209 is perfect for demanding communications applications, with AC performance that includes 77.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±5.5LSB INL, ±1LSB DNL (no missing codes).

The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed busses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.

LTC2209 Related Parts

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