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LTC2208-14 Datasheet

LTC2208-14 Datasheet

14-Bit, 130Msps ADC
Part No.: LTC2208-14
Page: 28 Pages
Size: 716 KB
Manufacturer: Linear Technology
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Views: 1
Update Time: 2023-11-14 15:54:23
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LTC2208-14 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2208CUP-14#PBF Tube 40 LTC2208UP-14 1 48 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208CUP-14#TRPBF Reel 2000 LTC2208UP-14 1 48 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208CUP-14#TRMPBF Reel 500 LTC2208UP-14 1 48 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208IUP-14#PBF Tube 40 LTC2208UP-14 1 48 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208IUP-14#TRPBF Reel 2000 LTC2208UP-14 1 48 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208IUP-14#TRMPBF Reel 500 LTC2208UP-14 1 48 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2208-14 Datasheet(PDF)

LTC2208-14 Datasheet(Picture)

LTC2208-14 Features

  • Sample Rate: 130Msps
  • 77.1dBFS Noise Floor
  • 98dB SFDR
  • SFDR >81dB at 250MHz (1.5VP-P Input Range)
  • PGA Front End (2.25VP-P or 1.5VP-P Input Range)
  • 700MHz Full Power Bandwidth S/H
  • Optional Internal Dither
  • Optional Data Output Randomizer
  • LVDS or CMOS Outputs
  • Single 3.3V Supply
  • Power Dissipation: 1.32W
  • Clock Duty Cycle Stabilizer
  • Pin Compatible 16-Bit Version
  • 64-Pin (9mm × 9mm) QFN Package

LTC2208-14 Applications

  • Telecommunications
  • Receivers
  • Cellular Base Stations
  • Spectrum Analysis
  • Imaging Systems
  • ATE

LTC2208-14 Description

The LTC2208-14 is a 130Msps, sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end.

The LTC2208-14 is perfect for demanding communications applications, with AC performance that includes 77.1dBFS Noise Floor and 98dB spurious free dynamic range (SFDR). Ultralow jitter of 70fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL (no missing codes).

The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.

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