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LTC2208 Datasheet

LTC2208 Datasheet

16-Bit, 130Msps ADC
Part No.: LTC2208
Page: 32 Pages
Size: 967 KB
Manufacturer: Linear Technology
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Views: 4
Update Time: 2023-11-14 15:08:59
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LTC2208 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2208CUP#PBF Tube 40 LTC2208UP 1 64 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208CUP#TRPBF Reel 2000 LTC2208UP 1 64 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208CUP#TRMPBF Reel 500 LTC2208UP 1 64 0°C ~ 70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208IUP#PBF Tube 40 LTC2208UP 1 64 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208IUP#TRPBF Reel 2000 LTC2208UP 1 64 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2208IUP#TRMPBF Reel 500 LTC2208UP 1 64 -40°C ~ 85°C 64-Lead (9mm × 9mm) Plastic QFN  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2208 Datasheet(PDF)

LTC2208 Datasheet(Picture)

LTC2208 Features

  • Sample Rate: 130Msps
  • 78dBFS Noise Floor
  • 100dB SFDR
  • SFDR >83dB at 250MHz (1.5VP-P Input Range)
  • PGA Front End (2.25VP-P or 1.5VP-P Input Range)
  • 700MHz Full Power Bandwidth S/H
  • Optional Internal Dither
  • Optional Data Output Randomizer
  • LVDS or CMOS Outputs
  • Single 3.3V Supply
  • Power Dissipation: 1.25W
  • Clock Duty Cycle Stabilizer
  • Pin Compatible 14-Bit Version 130Msps:
  • 64-Pin (9mm × 9mm)QFN Package

LTC2208 Applications

  • Telecommunications
  • Receivers
  • Cellular Base Stations
  • Spectrum Analysis
  • Imaging Systems
  • ATE

LTC2208 Description

The LTC2208 is a 130Msps, sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700MHz. The input range of the ADC can be optimized with the PGA front end.

The LTC2208 is perfect for demanding communications applications, with AC performance that includes 78dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4LSB INL, ±1LSB DNL (no missing codes) over temperature.

The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycle.

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