| Part No.： | LTC2151-12 |
| Page： | 30 Pages |
| Size： | 679 KB |
| Manufacturer： | Linear Technology |
| Logo： |  |
| Views： | 0 |
| Update Time： | 2024-12-05 21:04:04 |
| DataSheet： | Download |
| Part No. | Packing | SPQ | Marking | MSL | Pins | Temp Range | Package Description | Buy |
| LTC2151CUJ-12#PBF | Tube | 61 | LTC2151UJ-12 | 1 | 40 | 0°C ~ 70°C | 40-Lead (6mm × 6mm) Plastic QFN | |
| LTC2151CUJ-12#TRPBF | Reel | 2000 | LTC2151UJ-12 | 1 | 40 | 0°C ~ 70°C | 40-Lead (6mm × 6mm) Plastic QFN | |
| LTC2151IUJ-12#PBF | Tube | 61 | LTC2151UJ-12 | 1 | 40 | -40°C ~ 85°C | 40-Lead (6mm × 6mm) Plastic QFN | |
| LTC2151IUJ-12#TRPBF | Reel | 2000 | LTC2151UJ-12 | 1 | 40 | -40°C ~ 85°C | 40-Lead (6mm × 6mm) Plastic QFN |
The LTC2151-12 are a family of 210Msps 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 68.5dB SNR and 90dB spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to undersample high input frequencies with good performance. The latency is only five clock cycles.
DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.54LSBRMS.
The digital outputs are double-data rate (DDR) LVDS.
The ENC+ and ENC– inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
