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LTC2145-14 Datasheet

LTC2145-14 Datasheet

14-Bit, 125Msps Low Power Dual ADCs
Part No.: LTC2145-14
Page: 38 Pages
Size: 647 KB
Manufacturer: Linear Technology
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Update Time: 2024-12-21 10:01:08
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LTC2145-14 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2145CUP-14#PBF Tube 40 LTC2145UP-14 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2145CUP-14#TRPBF Reel 2000 LTC2145UP-14 1 64 0°C ~ 70°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2145IUP-14#PBF Tube 40 LTC2145UP-14 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
LTC2145IUP-14#TRPBF Reel 2000 LTC2145UP-14 1 64 -40°C ~ 85°C 64-Lead QFN (9mm x 9mm x 0.75mm)  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2145-14 Datasheet(PDF)

LTC2145-14 Datasheet(Picture)

LTC2145-14 Features

  • Two-Channel Simultaneously Sampling ADC
  • 73.1dB SNR
  • 90dB SFDR
  • Low Power: 189mW/149mW/113mW Total 95mW/75mW/57mW per Channel
  • Single 1.8V Supply
  • CMOS, DDR CMOS, or DDR LVDS Outputs
  • Selectable Input Ranges: 1VP-P to 2VP-P
  • 750MHz Full Power Bandwidth S/H
  • Optional Data Output Randomizer
  • Optional Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Serial SPI Port for Configuration
  • 64-Pin (9mm × 9mm) QFN Package

LTC2145-14 Applications

  • Communications
  • Cellular Base Stations
  • Software Defined Radios
  • Portable Medical Imaging
  • Multi-Channel Data Acquisition
  • Nondestructive Testing

LTC2145-14 Description

The LTC2145-14 are 2-channel simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.1dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.08psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is 1.2LSBRMS.

The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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