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LTC2142-12 Datasheet

LTC2142-12 Datasheet

12-Bit, 65Msps Low Power Dual ADCs
Part No.: LTC2142-12
Page: 38 Pages
Size: 1162 KB
Manufacturer: Linear Technology
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Views: 1
Update Time: 2024-04-23 11:17:35
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LTC2142-12 Datasheet Applicable Part

Part No. Packing SPQ Marking MSL Pins Temp Range Package Description Buy
LTC2142CUP-12#PBF Tube 40 LTC2142UP-12 1 64 0°C ~70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2142CUP-12#TRPBF Reel 2000 LTC2142UP-12 1 64 0°C ~70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2142CUP-12#TRMPBF Reel 500 LTC2142UP-12 1 64 0°C ~70°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2142IUP-12#PBF Tube 40 LTC2142UP-12 1 64 -40°C ~85°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2142IUP-12#TRPBF Reel 2000 LTC2142UP-12 1 64 -40°C ~85°C 64-Lead (9mm × 9mm) Plastic QFN  
LTC2142IUP-12#TRMPBF Reel 500 LTC2142UP-12 1 64 -40°C ~85°C 64-Lead (9mm × 9mm) Plastic QFN  
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

LTC2142-12 Datasheet(PDF)

LTC2142-12 Datasheet(Picture)

LTC2142-12 Features

  • 2-Channel Simultaneously Sampling ADC
  • 70.8dB SNR
  • 89dB SFDR
  • Low Power: 92mW/65mW/48mW Total 46mW/33mW/24mW per Channel
  • Single 1.8V Supply
  • CMOS, DDR CMOS, or DDR LVDS Outputs
  • Selectable Input Ranges: 1VP-P to 2VP-P
  • 750MHz Full Power Bandwidth S/H
  • Optional Data Output Randomizer
  • Optional Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Serial SPI Port for Configuration
  • 64-Pin (9mm × 9mm) QFN Package

LTC2142-12 Applications

  • Communications
  • Cellular Base Stations
  • Software Defined Radios
  • Portable Medical Imaging
  • Multi-Channel Data Acquisition
  • Nondestructive Testing

LTC2142-12 Description

The LTC2142-12 are 2-channel simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 70.8dB SNR and 89dB spurious free dynamic range (SFDR). Ultralow jitter of 0.08psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.3LSBRMS.

The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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